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CMOS

Process nameProcess DescriptionApplication, electrical parameters
5 V, 1.5 mm CMOS, 1 Poly, 1 , Poly- resistors CMOS15B / CMOS15BYPhotomasks, pcs.17
Design rules, mm1.5
Substrate: Boron/P-type/Res 12; Phos/N-type/Res4.5
Epi layer no/ Phos/N-type/Thk 8/Res 4.52 wells
N/P-well depth, mm5/6Supply voltage controller IC
-type Poly resistorsNMOS:
Bipolar vertical NPN transistor
Gate SiO2, Â250PMOS:
Interlayer dielectric: BPSGVtp= -0.5 / -0.6 V, Usd >10 V
NMOS/PMOS channel length, mm1.7
N&P LDD- drains
Pitch Poly, mm2.5
Contacts, mm1.3
Pitch Me, mm3.5
10 V, 3,0 mm Bi-CMOS, local n+, p+ - buried layers, Locos+ p-n junction isolation, 2 Poly, 1 e, specifically resistant, CMOS30Y-10
Photomasks, pcs18
Design rules, mm3.0
Substrate:Boron/P-type/Res 12Serial interface LSIC, RS-485 standard;
N+/P+ buried layersVDD = 5 V, Vin/ Vout (7 12)V
Epi layerPhos/N-type/Thk 20/Res 4.5specifically resistant
N/P-well depth, mm6/7
Gate SiO2, Â425NMOS: Vtn= (1.0 0.2)V
Interlayer dielectric:BPSGUsd >16 V
Channel length:PMOS: Vtp= (0.80.2)V
NMOS/PMOS, mm3.3/3.5Usd >16 V
Pitch Poly, mm5
Contacts, mm5
Pitch Me, mm6
3-5 V, 0.8 mm CMOS, 1 Poly (2 Poly), 2 Me CMOS08D
Photomasks, pcs.16(17)
Design rules, mm0.8
Substrate: Phos/N-type/Res 4.5 or
Bor/P-type/Res 122 wellsIC for telecommunication (SLIC)
N/P-well depths, mm4/4Customized IC, VDD 3 V 5 V
Interlayer dielectric:BPSG
Gate SiO2, Â130/ 160
channel lengthNMOS:
NMOS/PMOS, mm0.9/ 1.0Vtn=0.6 V, Usd >10 V
N&P LDD- drainsPMOS:
Me ITi-TiN/Al-Si/TiNVt=-0.8 V, Usd >10 V
Pitch Poly, mm1.9
Contacts 1, mm0.9
Pitch Me 1, mm2.2
Me 2Al-Si/TiN
Contacts 2, mm0.9
Pitch Me 2, mm2.4

Bipolar CDMOS

Process nameProcess DescriptionApplication, electrical parameters
200 V, with p-n junction isolation,1 Poly, 1 Me, NDMOS/PDMOS high-voltage transistors BCDMOS30-200Photomasks, pcs19
Mean design rule,mm4.0
EPI WAFER:Small -scale integration analogue IC, VDD < 210 V
Epi layer: Phos/ N-type/ Thk 27/ Res 8
Buried layers: Sb/N-type/Thk 30/Res 5.5; Boron/P-type/Thk 300/Res2.0
Substrate: Boron/ P-type/ Thk 460/ Res 60/ Orientation (100)NPN Vertical: bn =70 U=50 V
Isolation:p-n junctionNDMOS: Vtn= 2.0 V
P-well depth, mm6.5Usd >200 V
NDMOS base depth, mm3.0PDMOS: Vtp= -1.0 V
Gate SiO2, Â900Usd >200 V
NPN p-base depth, mm2.5NMOS: Vtn= 1.5 V , Usd >20 V
N+emitter depth, mm0.8
Interlayer dielectric low temp. PCGResistors in layer:
0,55mm +SIPOS 0.1mm + low temp. PCG1.1 mmNPN base, -drain, Poly
Channel length (gate):
NDMOS/PMOS, mm6Capacitors: Poly-Si (SiO2 900 Â)
Pitch Poly, mm8Poly-Al (SiO2 1600 Â)
Contacts, mm4
Pitch Me, mm12
90 V, p-n junction isolation, 1 Poly, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors BCDMOS30-90
Small and medium-scale integration analogue IC, VDD < 90 V
Photomasks, pcs.19
Mean design rule,mm4.0
EPI WAFER:NPN Vertical:
Epi layer: Phos/ N-type/ Thk 12/ Res 1.5;bn =50 U=20 V
Buried layers: Sb/N-type/Thk 20/Res 6; Boron/P-type/Thk 250/Res2.0PNP Lateral:
Substrate: Boron/ P-type/ Thk 460/ Res 12/ Orientation (100)b =25 U=20 V
Isolation:p-n junctionLNDMOS Vtn= 2.0 V
P-well depth, mm6.5Usd >90 V
NDMOS base depth, mm2.5LPDMOS: Vtp= -1.4 V
Gate SiO2, Â750Usd >90 V
NPN p-base depth, mm2.5NMOS: Vtn= 1.2 V, Usd >18 V
N+emitter depth, mm0.5PMOS: Vtp= 1.5 V, Usd >18 V
Interlayerdielectric -
BPSG, mm0.8
Channel length (gate):
NMOS/PMOS, mm7Resistors in layer:
Contacts, mm2NDMOS base, -drain, Poly
Pitch Me, mm8Capacitors: Poly-Si (SiO2 750Â)
Poly-Al (SiO2 8000 Â)

Bipolar CDMOS

Process nameProcess DescriptionApplication, electrical parameters
200 V, with p-n junction isolation, 1 Poly, 1 Me, NDMOS/PDMOS high-voltage transistors BCDMOS30-200Photomasks, pcs.19
Mean design rule,mm4.0
Epi layer: Phos/ N-type/ Thk 27/ Res 8;Small -scale integration analogue IC, VDD < 210 V
Buried layers: Sb/N-type/Thk 30/Res 5.5; Boron/P-type/Thk 300/Res2.0NPN Vertical:
Substrate: Boron/ P-type/ Thk 460/ Res 60/ Orientation (100)bn =70 U=50 V
Isolation:p-n junctionNDMOS: Vtn= 2.0 V
P-well depth, mm6.5Usd >200 V
NDMOS base depth, mm3.0PDMOS: Vtp= -1.0 V
Gate SiO2, ?900Usd >200 V
NPN p-base depth, mm2.5NMOS: Vtn= 1.5 V , Usd >20 V
N+emitter depth, mm0.8
Interlayer dielectric low temp. PCGResistors in layer:
0,55mm +SIPOS 0.1mm + low temp. PCG1.1 mmNPN base, -drain, Poly.
Channel length (gate):
NDMOS/PMOS, mm6Capacitors: Poly-Si (SiO2 900 ?)
Pitch Poly, mm8Poly-Al (SiO2 1600 ?)
Contacts, mm4
Pitch Me, mm12
90 V, p-n junction isolation, 1 Poly, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors BCDMOS30-90Small and medium-scale integration analogue IC, VDD < 90 V
Photomasks, pcs.19
Mean design rule,mm4.0
EPI WAFER:NPN Vertical:
Epi layer: Phos/ N-type/ Thk 12/ Res 1.5;bn =50 U=20 V
Buried layers: Sb/N-type/Thk 20/Res 6; Boron/P-type/Thk 250/Res2.0PNP Lateral:
Substrate: Boron/ P-type/ Thk 460/ Res 12/ Orientation (100)b =25 U=20 V
Isolation:p-n junctionLNDMOS Vtn= 2.0 V
P-well depth, mm6.5Usd >90 V
NDMOS base depth, mm2.5LPDMOS: Vtp= -1.4 V
Gate SiO2, ?750Usd >90 V
NPN p-base depth, mm2.5NMOS: Vtn= 1.2 V, Usd >18 V
N+emitter depth, mm0.5PMOS: Vtp= 1.5 V, Usd >18 V
Interlayerdielectric -VNDMOS: Vtn= 2.0 V
BPSG, mm0.8Usd >70 V
Channel length (gate):Resistors in layer:
NMOS/PMOS, mm7NDMOS base, -drain, Poly
Contacts, mm2Capacitors: Poly-Si (SiO2 750?)
Pitch Me, mm8Poly-Al (SiO2 8000 ?)

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